No products
JEDEC JESD82-6ADEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 11/01/2004
JEDEC JESD22-A103CHIGH TEMPERATURE STORAGE LIFEstandard by JEDEC Solid State Technology Association, 11/01/2004
JEDEC JESD82-7ADEFINITION OF THE SSTU32864 1.8-V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 10/01/2004
JEDEC JESD82-11DEFINITION OF 'CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 09/01/2004
JEDEC JESD60AA PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESSstandard by JEDEC Solid State Technology Association, 09/01/2004
JEDEC JESD 22-B107CMARKING PERMANENCYstandard by JEDEC Solid State Technology Association, 09/01/2004
JEDEC JESD75-5SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 07/01/2004
JEDEC JESD22-A106BTHERMAL SHOCKstandard by JEDEC Solid State Technology Association, 06/01/2004
JEDEC JEP84ARECOMMENDED PRACTICE FOR MEASUREMENT OF TRANSISTOR LEAD TEMPERATUREstandard by JEDEC Solid State Technology Association, 06/01/2004
JEDEC JS 9702IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)standard by JEDEC Solid State Technology Association, 06/01/2004
JEDEC JESD24-12THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)Amendment by JEDEC Solid State Technology Association, 06/01/2004
JEDEC JESD 22-A111EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICESstandard by JEDEC Solid State Technology Association, 05/01/2004