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JEDEC JESD8-19POD18 - 1.8 V Pseudo Open Drain I/Ostandard by JEDEC Solid State Technology Association, 12/01/2006
JEDEC JESD 82-22INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINESstandard by JEDEC Solid State Technology Association, 11/01/2006
JEDEC JESD89AMEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICESstandard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JESD22-B117ASOLDER BALL SHEARstandard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JESD 46CCUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERSstandard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JESD82-14ADEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONSstandard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JEP121AREQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATIONstandard by JEDEC Solid State Technology Association, 10/01/2006
JEDEC JEP179DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATIONstandard by JEDEC Solid State Technology Association, 06/01/2006
JEDEC JESD8-7AADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITstandard by JEDEC Solid State Technology Association, 06/01/2006
JEDEC JP 002CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINEstandard by JEDEC Solid State Technology Association, 03/01/2006
JEDEC JESD202METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESSstandard by JEDEC Solid State Technology Association, 03/01/2006
JEDEC JESD75-6PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 03/01/2006