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Describes a high-performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on IEC 60297. Note: -1.This bus is similar to the VME bus. 2.For the price of this publication, please consult the ISO/IEC price-code list.
| Author | IEC |
|---|---|
| Editor | CEI |
| Document type | Standard |
| Format | File |
| Edition | 2.0 |
| ICS | 31.080.01 : Semiconductor devices in general 35.160 : Microprocessor systems 35.200 : Interface and interconnection equipment |
| Number of pages | 561 |
| Replace | IEC 60821 (1987) |
| Cross references | DIN EN 60821 (1994-09), MOD |
| Modified by | IEC 60821 AMD 1 (1999-01) |
| Year | 1990 |
| Document history | IEC 60821 (1991-12) |
| Country | Switzerland |
| Keyword | IEC60821;IEC 60821:1991 |