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IEC 63011-1 (2018-11)
IEC 63011-1:2018 Integrated circuits - Three dimensional integrated circuits - Part 1: TerminologyMore info
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
| Author | IEC |
|---|---|
| Editor | CEI |
| Document type | Standard |
| Format | File |
| Edition | 1.0 |
| ICS | 31.200 : Integrated circuits. Microelectronics |
| Number of pages | 24 |
| Year | 2018 |
| Country | Switzerland |
| Keyword | IEC63011;IEC 63011-1:2018 |