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This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the external environment. JESD12-6 is intended to provide the ASIC manufacturer and user with a common set of signal interface levels. The standard defines interface levels for 5 volt operation.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 35.200 : Interface and interconnection equipment |
| Number of pages | 12 |
| Year | 1990 |
| Document history | |
| Country | USA |
| Keyword | EIA JESD 12;EIA 12;EIA 12.6;12;EIA JESD12-6 |