EIA JEP 139:2000 (R2012)

This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. If the metallization is a single-alloy component, such as AlSi or AlCu, the failure criterion of the method is an open-circuit of the test structure. The failure criterion for layered metallizations with refractory shunt layers (such as titanium (Ti), titanium nitride (TiN), tungsten (W), etc.) is a preselected percent increase in resistance of the test structure. The method assumes that void growth and therefore resistance changes can be modeled, as described by Rauch and Sullivan [1, 2], to obtain an acceleration factor for void growth. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking.