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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 31.200 : Integrated circuits. Microelectronics |
| Number of pages | 30 |
| Replace | EIA JESD 8-9 (1998-09) |
| Modified by | EIA JESD 8-9B Errata (2002-10-18) |
| Year | 2002 |
| Document history | EIA JESD 8-9B (2002-05) |
| Country | USA |
| Keyword | EIA JESD 8;EIA 8;EIA 8.9B;8;EIA JESD8-9B |