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EIA JESD 8-8:1996
Stub Series Terminated Logic for 3.3 Volts (SSTL-3)More info
This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 35.200 : Interface and interconnection equipment |
| Number of pages | 19 |
| Year | 1990 |
| Document history | |
| Country | USA |
| Keyword | EIA JESD 8;EIA 8;EIA 8.8;8;EIA JESD8-8 |